library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;

entity counter is

generic(N : natural := 8)
port(
  reset_n : in std_logic;
  clk     : in std_logic;
  enable  : in std_logic;
  value   : out unsigned(N-1 downto 0)
);

end counter;

architecture rtl of counter is

signal count : unsigned(N-1 downto 0);

begin

counting: process(reset_n,clk)
begin
  if reset_n='0' then
    count <= to_unsigned(0,N);
  elsif rising_edge(clk) then
    if enable='1' then
      count <= count + 1;
    end if
  end if;
end process;

value <= count;

end rtl;