library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;

entity tb is end tb;

architecture bhv of tb is

signal stdlv : std_logic_vector(31 downto 0);
signal u32   : unsigned(11 downto 0);
signal u16   : unsigned(11 downto 0);
signal u12   : unsigned(11 downto 0);
signal s12   : signed(11 downto 0);

begin

stdlv <= x"deedbeef";
u32   <= unsigned(stdlv);
u12   <= resize(u32,12);

s12 <= resize(signed(stdlv),12);

u16 <= resize(to_unsigned(42,12),16);

end bhv;