library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;

entity tb is end tb;

architecture bhv of tb is

constant HALF_PERIOD : time := 5 ns; --100Mhz
signal running : boolean := true;
signal clk : std_logic := '0';

begin

-- clock generator
clk <= not clk after HALF_PERIOD when running else clk;

-- asynchronous reset
reset_n  <= '0','1' after 123 ns;

-- circuit under test
DUT: entity work.my_circuit(RTL)
  port map(
    reset_n => reset_n,
    clk => clk,
    input_a => a,
    output_f => f
  );

-- stimuli
stim:process
begin
  report "starting simulation";
  wait until reset_n='0';

  report "waiting 100 clock cycles";
  for i in 0 to 100 loop
    wait until rising_edge(clk);
  end loop;

  report "starting test vector";
  wait until rising_edge(clk);
  a <= to_unsigned(1,8);

  wait until rising_edge(clk);
  a <= to_unsigned(2,8);

  report "waiting 100 clock cycles";
  for i in 0 to 100 loop
    wait until rising_edge(clk);
  end loop;

  running <= false;
  wait; --forever
end process;

end bhv;