library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
entity bram is generic(
data_width: integer:= 8; address_width:integer := 8; mem_depth: integer:= 256);
port (
clk : in std_logic; we : in std_logic; datain : in std_logic_vector(data_width-1 downto 0); address : in unsigned(address_width-1 downto 0); dataout: out std_logic_vector(data_width-1 downto 0));
end bram;
architecture rtl of bram is
type mem_type is array (mem_depth-1 downto 0) of std_logic_vector (data_width-1 downto 0); signal mem: mem_type; signal raddress : unsigned(address_width-1 downto 0);
begin l0: process (clk, we, address)
begin if (clk = '1' and clk'event) then raddress <= address; if (we = '1') then mem(to_integer(raddress)) <= datain; end if; end if; end process;
l1: process (clk, address)
begin if (clk = '1' and clk'event) then dataout <= mem(to_integer(address)); end if; end process;
end rtl;