library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;

entity fsm is

port(
  reset_n : in std_logic;
  clk     : in std_logic;
  go      : in std_logic;
  f       : out unsigned(7 downto 0)
);

end fsm;

architecture rtl_1 of fsm is

type state_type is (IDLE,PING,PONG);
signal state_r,state_c : state_type;
signal output_f : unsigned(7 downto 0);

begin

tick : process(reset_n,clk)
begin
  if reset_n='0' then
    state_r <= IDLE;
  elsif rising_edge(clk) then
    state_r <= state_c;
  end if;
end process;

comb : process(go,state_r)
  begin
    state_c <= state_r; --default assigment
    case state_r is
      when IDLE =>
        if go='1' then
          state_c <= PING;
        end if;
      when PING =>
        state_c <= PONG;
      when PONG =>
        state_c <= PING;
      when others =>
        null;
    end case;
end process;

output_gen : process(reset_n,clk)
 begin
   if reset_n='0' then
     output_f <= (others=>'0');
   elsif rising_edge(clk) then
     if state_r=PONG then
       output_f <= output_f + 1;
     end if;
   end if;
 end process;

f <= output_f;

end rtl_1;