library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
entity example is
generic(N : natural := 8) port( reset_n : in std_logic; clk : in std_logic; enable : in std_logic; );
end example ;
architecture rtl of example is
-- constant CST : natural := 42; -- type regs is array(0 to 10) of ... -- signal x : unsigned(N-1 downto 0);
begin
-- synchronous (a.k.a 'clocked') process process(reset_n,clk) begin if reset_n='0' then -- ... elsif rising_edge(clk) then if enable='1' then -- ... end if end if; end process; -- conditional assignment z <= a when c1 else b when c2 else d; -- component instanciation inst_0: use work.decoder(RTL) generic map(param => 42) port map( reset_n => reset_n, clk => clk );
end rtl;