library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;

entity tb is end tb;

architecture bhv of tb is

constant HALF_PERIOD : time := 5 ns; --100Mhz
signal running : boolean := true;
signal clk : std_logic := '0';

begin

-- clock generator
clk <= not clk a after HALF_PERIOD when running else clk;

end bhv;